The present invention relates to a semiconductor device, and more particularly, to a semiconductor device capable of improving a margin of a storage node contact plug and a method of manufacturing the same.
Most electronic appliances today include semiconductor devices. The semiconductor devices include electronic elements such as transistors, resistors and capacitors, etc. The electronic elements are designed to perform partial functions of the electronic appliances which are integrated on a semiconductor substrate. For example, electronic appliances such as computers or digital cameras include memory chips for storing information and processing chips for processing the information control and the memory chips. These processing chips include the electronic elements integrated on the semiconductor substrate.
On the other hands, the semiconductor devices need to be more highly integrated in order to satisfy the high performance and low prices that user's demand. As the integration degree of the semiconductor device is increased, design rules are scaled down and patterns of the semiconductor device are miniaturized. As the semiconductor device becomes largely miniaturized and highly integrated, the total dimension of the chip is increased in proportion to the increment in the memory capacity, but the dimension of a cell area in which patterns of the semiconductor device are formed in is substantially reduced. Accordingly, in order to ensure the desired memory capacity, because many patterns should be formed in the defined area, the fine patterns where the critical dimensions are scaled down should be formed.
Various fine pattern formation methods have been developed to lower the threshold value of the resolution. These methods include a method using a phase shift mask as a photo mask, a Contrast Enhancement Layer (CEL) method which forms a separate layer for improving an image contrast on a thin wafer, a Tri Layer Resister (TLR) method where an intermediate layer such as a spin on glass (SOG) is interposed between two photoresist layers and a silylation method which selectively implants silicons in the upper portion of the photoresist layer.
On the other hands, the contacts for connecting upper and lower interconnections are largely affected by the design rule as compared with the line/space patterns. That is, as the device is highly integrated, the size of the device and the distance between neighboring interconnections are reduced. According to this, the aspect ratio which is the ratio of the depth to the diameter of the contact is increased and it is difficult to form contacts. Therefore, the contact formation process is very important in manufacturing the high integration semiconductor device. Accordingly, when the contact holes are formed in the high integration semiconductor device having multi-layered interconnections, because the accurate and strict alignment is demanded, the process margin is reduced or the process should be performed without margin.
In particular, a self align contact (SAC) fail between the landing plug and a gate or between the landing plug and a recess gate occur in a landing plug formation process so that the yield is lowered. According to this, the technique for preventing the SAC fail with the landing pad by changing a gate or a recess gate structure to a buried gate structure is suggested. However, the SAC fail between the storage node contact plug and a bit line still generated in the buried structure and the disconnection between the storage node contact plug and the landing plug is also generated.